1. Field of the Invention
The present invention relates to a device for directly accessing a memory, forming a part of a computer system, independently of a central processing unit, and more specifically, to a memory accessing device which is connected to a bus for connecting a central processing unit, buffer storing units such as cache memories, etc. and which accesses a memory independently of the central processing unit, with a cache memory being kept consistent with the main memory storage.
2. Description of the Prior Art
The configuration of a central processing unit (hereinafter referred to as a CPU), having a built-in primary cache memory comprising a memory capable of being accessed rapidly by the CPU, and further having a secondary cache memory connected to the main storage unit, is very popular for improving the performance of a computer system. The primary cache memory is a high-speed, expensive, and relatively small capacity memory, while the secondary cache memory is a lower-speed and much cheaper memory, but is still faster and more expensive than the main memory storage.
FIG. 1 shows the configuration of a computer system which includes primary and secondary cache memories. The system shown in FIG. 1 comprises a CPU 2, which includes a primary cache memory 3, a secondary cache memory 4, a main storage unit 5, and an input/output unit 6 (hereinafter abbreviated to I/O unit). The CPU 2 and the secondary cache memory 4 are connected through a processor bus 8 (hereinafter abbreviated to a P bus). The secondary cache memory 4, the main storage unit 5, and the I/O unit 6 are connected through a memory bus 9 (hereinafter abbreviated to an M bus). The I/O unit 6 can perform a DMA (direct memory access) data transmission to and from the main storage unit 5 through the M bus 9.
The primary cache memory 3 and the secondary cache memory 4 in the above described system configuration must be kept logically consistent with the main storage unit 5 regardless of their write-through control method, that is, a write-through control method or a copy-back (write-back) control method. In the write-through control method, for example, data are written from the primary cache memory 3 to the secondary cache memory 4 and then from the secondary cache memory 4 to the main storage unit 5 if a block address in which data is to be written is in the primary cache memory 3. In the copy-back control method, block data are written in the primary cache memory 3 or the secondary cache memory 4, and then the contents of the main storage unit 5 is updated by transmitting the block data to the main storage unit 5 when the updated block data is to be replaced. Thus, the cache memory is kept consistent with the main storage memory when data are written to the cache memory regardless of whether the write-through control method or the copy-back control method is used.
If the main storage unit is rewritten, the data in it should be kept consistent with the data in a cache memory. Therefore, for example, if a part of the contents of the main storage unit 5 is rewritten by the I/O unit 6 connected through the M bus 9, the secondary cache memory 4 monitors the addresses on the M bus 9. If the data at the address where data have been rewritten in the main storage unit 5 are entered in the secondary cache memory 4, the entry in the cache memory is invalidated to maintain consistency between the secondary cache memory 4 and the main storage unit 5.
Then, the secondary cache memory 4 must inform the primary cache memory 3 of the fact that the contents of the main storage unit 5 has been rewritten. Therefore, the secondary cache 4 outputs a monitor request signal for invalidating a cache entry in the primary cache memory 3, and outputs the address of the main storage unit 5 according to which data have been rewritten. If the primary cache memory 3 receives the monitor request signal and the address information, and the primary cache memory 3 has an entry at the address according to which the main storage unit 5 has been rewritten, the primary cache memory 3 invalidates the entry in the cache memory to maintain consistency between the primary cache memory 3 and the main storage unit 5.
There is another system provided with a memory accessing device for accessing a secondary cache memory and a main storage memory independently of the CPU 2. FIG. 2 shows the configuration of the computer system comprising a memory accessing device 1. The memory accessing device 1 is, for example, a vector process unit (VPU), etc. in which the primary cache memory accesses the secondary cache memory instead of requiring the arithmetic operation of the CPU 2 to perform a vector operation at a high speed.
The memory accessing device 1 requests the right to use the P bus 8, indicated by a bus use right request signal 31, when an operation instruction is issued under control of the CPU 2.
In response to the request, a bus use right response signal 32 from the CPU 2 is asserted, and the memory accessing device 1 acquires the bus use right. Then, the device directly accesses a memory to perform a vector operation in a pipeline process.
Since the computer system has such a memory accessing device, a cache memory entry is invalidated to maintain consistency between the secondary cache memory 4 and the main storage unit 5. As in the case of FIG. 1, the cache memory entry is invalidated if the main storage unit 5 is rewritten by the I/O device 6, etc. on the M bus 9, when the memory accessing device 1 obtains the right to use the P bus 8 (obtains the bus use right of the P bus 8) and accesses the primary cache memory or the secondary cache memory. However, when the memory accessing device 1 obtains the bus use right of the P bus 8 for connecting the secondary cache memory 4 and the primary cache memory 3 in the CPU 2, the secondary cache memory 4 outputs an address on the P bus 8 to the primary cache memory 3. Accordingly, there arises a conflict between the secondary cache memory 4 and the memory accessing device 1 to output an address on the P bus 8, since usage of the P bus 8 is not managed. Therefore, it becomes impossible to inform the primary cache memory 3 of the fact that the contents of the main storage unit 5 have been rewritten. Thus, there has been a problem in that consistency cannot be successfully maintained.
To prevent such a bus use right conflict on the P bus 8, there is a method in which the secondary cache memory 4 controls the bus use right of the memory accessing device 1 described above. This method certainly prevents a conflict for use of the P bus, but anther problem, it takes much time to appropriately execute the bus arbitration (adjustment of bus use right, arises. For example, if the memory accessing device 1 is a vector processor for performing a pipeline process, a complicated sequence is required to interrupt the pipeline process.
Since the CPU 2 will be accessing the primary cache 3 if the system has to wait for the memory access unit 1 to complete its accessing operation, a problem has arisen in that an insignificant process is performed using the contents of the primary cache memory 3 without maintaining consistency between the main storage unit 5 and the cache memories.